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HD74AC175
Quad D-Type Flip-Flop
REJ03D0257-0200Z (Previous ADE-205-377 (Z)) Rev.2.00 Jul.16.2004
Description
The HD74AC175 is a high-speed quad D flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the D inputs is stored during the Low-to-High clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or D inputs, when Low.
Features
* Edge-Triggered D-Type Inputs * Buffered Positive Edge-Triggered Clock * Asynchronous Common Reset * True and Complement Output * Outputs Source/Sink 24 mA * Ordering Information
Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) FP-16DAV TTP-16DAV FP RP T EL (2,000 pcs/reel) EL (2,500 pcs/reel) ELL(2,000 pcs/reel)
HD74AC175AFPEL SOP-16 pin (JEITA) HD74AC175TELL TSSOP-16 pin
HD74AC175ARPEL SOP-16 pin (JEDEC) FP-16DNV
Notes: 1. Please consult the sales office for the above package availability. 2. The packages with lead-free pins are distinguished from the conventional products by adding V at the end of the package code.
Pin Arrangement
MR 1 Q0 2 Q0 3 D0 4 D1 5 Q1 6 Q1 7 GND 8 (Top view) 16 VCC 15 Q3 14 Q3 13 D3 12 D2 11 Q2 10 Q2 9 CP
Rev.2.00, Jul.16.2004, page 1 of 7
HD74AC175
Logic Symbol
D0 CP
D1
D2
D3
MR Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3
Pin Names
D0 to D3 CP MR Q0 to Q3 Q0 to Q 3 Data Inputs Clock Pulse Input Master Reset Input True Outputs Complement Outputs
Functional Description
The HD74AC175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual D inputs on the Low-to-High clock (CP) transition, causing individual Q and Q outputs to follow. A Low input on the Master Reset (MR) will force all Q outputs Low and Q outputs High independent of Clock or Data inputs. The HD74AC175 is useful for general logic applications where a common Master Reset and Clock are acceptable.
Truth Table
Inputs @ tn, MR = H Dn L H H: L: tn : tn + 1 High Voltage Level Low Voltage Level Bit Time before Clock Pulse : Bit Time after Clock Pulse Qn L H Outputs @ tn+1 Qn H L
Rev.2.00, Jul.16.2004, page 2 of 7
HD74AC175
Logic Diagram
MR CP D3 D2 D1 D0
D
Q
D
Q
D
Q
D
Q
CP Q CD
CP Q CD
CP Q CD
CP Q CD
Q3 Q3
Q2 Q2
Q1 Q1
Q0 Q0
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
Absolute Maximum Ratings
Item Supply voltage DC input diode current DC input voltage DC output diode current DC output voltage DC output source or sink current DC VCC or ground current per output pin Storage temperature Symbol VCC IIK VI IOK VO IO ICC, IGND Tstg Ratings -0.5 to 7 -20 20 -0.5 to Vcc+0.5 -50 50 -0.5 to Vcc+0.5 50 50 -65 to +150 Unit V mA mA V mA mA V mA mA C VI = -0.5V VI = Vcc+0.5V VO = -0.5V VO = Vcc+0.5V Condition
Recommended Operating Conditions
Item Supply voltage Input and output voltage Operating temperature Input rise and fall time (except Schmitt inputs) VIN 30% to 70% VCC Symbol VCC VI, VO Ta tr, tf Ratings 2 to 6 0 to VCC -40 to +85 8 V V C ns/V VCC = 3.0V VCC = 4.5 V VCC = 5.5 V Unit Condition
Rev.2.00, Jul.16.2004, page 3 of 7
HD74AC175
DC Characteristics
Item Symbol VIH Vcc (V) 3.0 4.5 5.5 VIL 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 VOL 5.5 3.0 4.5 5.5 3.0 4.5 Input leakage current Dynamic output current* Quiescent supply current IIN IOLD IOHD ICC 5.5 5.5 5.5 5.5 5.5 min. 2.1 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.58 3.94 4.94 -- -- -- -- -- -- -- -- -- -- Ta = 25C typ. 1.5 2.25 2.75 1.50 2.25 2.75 2.99 4.49 5.49 -- -- -- 0.002 0.001 0.001 -- -- -- -- -- -- -- max. -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.32 0.32 0.32 0.1 -- -- 8.0 Ta = -40 to +85C min. max. 2.1 -- 3.15 3.85 -- -- -- 2.9 4.4 5.4 2.48 3.80 4.80 -- -- -- -- -- -- -- 86 -75 -- -- -- 0.9 1.35 1.65 -- -- -- -- -- -- 0.1 0.1 0.1 0.37 0.37 0.37 1.0 -- -- 80 A mA mA A V VOUT = 0.1 V or VCC -0.1 V Unit Condition
Input Voltage
V
VOUT = 0.1 V or VCC -0.1 V
Output voltage
VOH
VIN = VIL or VIH IOUT = -50 A VIN = VIL or VIH IOH = -12 mA IOH = -24 mA IOH = -24 mA VIN = VIL or VIH IOUT = 50 A VIN = VIL or VIH IOL = 12 mA IOL = 24 mA IOL = 24 mA VIN = VCC or GND VOLD = 1.1 V VOHD = 3.85 V VIN = VCC or ground
*Maximum test duration 2.0 ms, one output loaded at a time.
AC Characteristics
Ta = +25C CL = 50 pF Min Typ Max 149 187 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 9.5 7.0 8.5 6.0 7.5 5.5 8.5 6.0 -- -- 12.0 9.0 13.0 9.5 12.5 9.0 11.0 8.5 Ta = -40C to +85C CL = 50 pF Min Max 139 187 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 -- -- 13.5 9.5 14.5 10.5 13.5 10.0 12.5 9.0 MHz ns ns ns ns
Item Maximum clock frequency Propagation delay CP to Qn or Qn Propagation delay CP to Qn or Qn Propagation delay MR to Qn Propagation delay MR to Qn Note:
Symbol fmax tPLH tPHL tPLH tPHL
VCC (V)*1 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
Unit
1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V
Rev.2.00, Jul.16.2004, page 4 of 7
HD74AC175
AC Operating Requirements
Ta = +25C CL = 50 pF Item Set-up time, HIGH or LOW Dn to CP Hold time, HIGH or LOW Dn to CP CP pulse width HIGH or LOW MR pulse width, LOW Recovery time MR to CP Note: Symbol VCC (V)*1 Typ tsu 3.3 2.0 th tw tw trec 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 1. Voltage Range 3.3 is 3.3 V 0.3 V Voltage Range 5.0 is 5.0 V 0.5 V 1.0 0 0 2.5 2.0 2.5 2.0 -2.0 -1.0 Ta = -40C to +85C CL = 50 pF Unit ns ns ns ns ns
Guaranteed Minimum 4.5 4.5 3.0 1.0 1.0 4.5 3.5 4.5 3.5 0.0 0.0 3.0 1.0 1.0 4.5 3.5 5.0 3.5 0.0 0.0
Capacitance
Item Input capacitance Power dissipation capacitance Symbol CIN CPD 4.5 45.0 Typ pF pF Unit VCC = 5.5 V VCC = 5.0 V Condition
Rev.2.00, Jul.16.2004, page 5 of 7
HD74AC175
Package Dimensions
As of January, 2003
10.06 10.5 Max 16 9
5.5
Unit: mm
1
*0.20 0.05
8
0.80 Max
2.20 Max
0.20 7.80 + 0.30 -
1.15
1.27
0.10 0.10
0 - 8
0.70 0.20
*0.40 0.06
0.15
0.12 M
Package Code JEDEC JEITA Mass (reference value) FP-16DAV -- Conforms 0.24 g
*Ni/Pd/Au plating
As of January, 2003
Unit: mm
9.9 10.3 Max 16 9
3.95
1 1.27 0.635 Max
8
0.11 0.14 + 0.04 - 1.75 Max
*0.20 0.05
0.10 6.10 + 0.30 -
1.08
0 - 8
+ 0.67 0.60 - 0.20
*0.40 0.06
0.15 0.25 M
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
FP-16DNV Conforms Conforms 0.15 g
Rev.2.00, Jul.16.2004, page 6 of 7
HD74AC175
As of January, 2003
Unit: mm
5.00 5.30 Max 16 9
4.40
1
*0.20 0.05
8 0.65 0.13 M 0.65 Max
*0.15 0.05
1.0 6.40 0.20 0 - 8 0.50 0.10
1.10 Max
0.10
0.07 +0.03 -0.04
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-16DAV -- -- 0.05 g
Rev.2.00, Jul.16.2004, page 7 of 7
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